This invention relates to the measurement of high-speed electrical characteristics of integrated circuit packages and other interconnect structures for interfacing with high-speed integrated circuits.
Predicting the performance of subnanosecond integrated circuits requires accurate measurement of the electrical characteristics of the package or other interconnect structure which interfaces the integrated circuit with the larger circuit of which it is a part. Such measurements are necessary because the electrical characteristics of the package or other interconnect structure can dominate the performance limits of a high-speed integrated circuit. Time domain reflectometry and network analysis measurements must typically be performed to determine the following electrical characteristics of such interconnect structures:
(a) loss by radiation into the surrounding dielectric; PA1 (b) electrical resonances caused by the interaction of parasitic capacitance and inductance in the signal path; PA1 (c) spectral dispersion when energy storage by parasitic capacitance and inductance causes higher frequencies to be attenuated more quickly, thereby degrading signal edges; and PA1 (d) cross coupling with neighboring lines when capacitive and inductive coupling causes pick-up of signals carried on a nearby conductor track. PA1 (a) some packages and other interconnect structures have terminals mechanically inaccessible to direct contact by a planar transmission line probe, either because the depth and width of a package well makes the internal terminals inaccessible or because the terminals are not sufficiently coplanar for effective simultaneous contact by such a probe; PA1 (b) different packages and other interconnect structures have a wide variety of signal and ground terminal spacings, which therefore require corresponding different probes with different signal and ground contact spacings to mechanically interface therewith; PA1 (c) the complex effects of various lengths, spacings, and multiplicities of interface structures, such as bond wires, used to connect the integrated circuit to the terminals of the interconnect structure cannot be included in the measurements. PA1 (d) a signal or power terminal of an interconnect structure, which is not located adjacent to any ground terminal, cannot be contacted effectively by a planar probe because the probe tip contact spacing cannot span the distance between the signal or power terminal and the nearest available ground terminal.
The principal problem with obtaining the foregoing measurements involves establishing an effective electrical connection to the terminals of the package or other interconnect structure. In the past, special purpose fixtures have been constructed for this purpose, but such fixtures require labor-intensive construction, provide little or no test configuration versatility for adaptation to different interconnect structures, and often introduce errors into the measurements because of their own electrical characteristics.
An improved approach which seeks to cure at least some of these deficiencies is described in Carlton, D. E. et al., "Accurate Measurement of High-Speed Package and Interconnect Parasitics," IEEE 1988 Custom Integrated Circuits Conference, Jan. 1988, vol. CH2584-1/88/000-0138, pp. 23.3.1-23.3.7. This article discusses the use of a planar transmission line probe, such as that described in U.S. Pat. No. 4,697,143, to contact the terminals of a package or other interconnect structure directly. This approach provides a less labor-intensive and more versatile connection system. It also provides a way of removing, by calibration, probe and cable-related errors from the measurements by using impedance standards with known electrical characteristics such as resistors, short-circuits, and through-connections mounted on an "impedance standard substrate," as described further in Cascade Microtech, Inc., "Electrical Operation," Model 42-42D Microwave Probe Station Instruction Manual, chap. 4, at 4-1 to 4-42 (1987). The mathematics for the calibration operation are well known in the industry and are described, for example, in the foregoing Cascade Microtech instruction manual and in U.S. Pat. No. 4,858,160 which are incorporated herein by reference, as well as in the following technical articles which are also incorporated herein by reference: Swanson, D., "Ferret Out Fixture Errors with Careful Calibration," Microwaves, Jan. 1980, at 79-84; Fitzpatrick, J., "Error Models for Systems Measurement," Microwave Journal, May 1978, at 63-66.
However, even with the foregoing improved approach, the following significant deficiencies remain: